Individual Control of Paralleled SiC-MOSFETs with Nano-Second Level Switching Timing Synchronization

This paper describes a control method that feeds back the switching timing of SiC-MOSFETs connected in parallel to suppress switching current concentration. The voltage generated by the inductance of the source electrode during switching is detected by the detection circuit and used as a feedback signal. Compare the time difference of feedback signals for each SiC-MOSFET with 1nane-second (nsec) resolution using FPGA. Current concentration can be suppressed by adjusting the timing of the gate signals so that the time difference is minimized automatically. This control is also effective against changes in SiC-MOSFET characteristics over time, such as gate deterioration and increase in thermal resistance occurred by power cycles. The effectiveness of the developed control on gate degradation and increased thermal resistance is demonstrated through experiments.