Experimental Demonstration of the Double-Trench, Buried-P JTE Edge Termination with Short Edge Width and High dV/dt Capability for 1200 V-class SiC Devices

A double trench, buried-P junction termination extension (DTBP-JTE) edge termination structure for 1200 V-class SiC devices is experimentally demonstrated. The proposed structure features a short JTE followed by two floating buried-P layers at the bottom of the double trenches. Process module of JTE and buried-P patterning has been developed and optimized to implement both the JTE and floating buried-P layers underneath the trenches simultaneously. Sidewall spacer of hard mask is adopted to eliminate thin P-layers at the trench sidewall, and thus ensure that the buried-P layers keep floating. Experimental results show that the fabricated DTBP-JTE edge termination achieves a BV of 1416 V with an edge width of only 19 μm. By comparison, the conventional guard-ring structure has a BV of 1358 V with an edge width of 103um. The DTBP-JTE achieves higher BV with a five times shorter edge width. Furthermore, the DTBP-JTE can pass the high dV/dt test under the condition of 88 V/ns with a bus voltage of 1200 V. Therefore, the DTBP-JTE achieves a better tradeoff between breakdown voltage and edge width without sacrificing the high dV/dt capability.