Influence of SiC MOSFET Gate Technologies on Imbalanced Performance in Hard Switching Parallel Operation

This study examines the impact of commercially available SiC MOSFET gate technologies (trench and planar) on dynamic performances in parallel operation, thus the spread of device parameters that affect these performances. The study also delves into the fabrication differences between the gate technologies and identifies manufacturing tolerances that influence the parameter variation in TMOS and DMOS. Initially, a design of experiment (DoE) was conducted to determine which gate technology is more susceptible to process deviations. To validate the DoE results, the device parameters distribution of 70 samples from four commercially available SiC MOSFETs (two trench and two planar) in TO-247 4-pin packages were characterized. Additionally, double-pulse tests were performed to demonstrate the actual effect of these parameters on dynamic current imbalances. Through the analysis of a sufficient number of samples, this study provides an understanding of the influence of SiC MOSFET technologies on parameter variations. This will ultimately help determine the most suitable gate technology to achieve reliable parallel operation, specifically in SiC-based hard-switching high-power converters.