Novel Approach to Mitigate Parasitic Oscillation of Power Modules with Parallel Connected SiC-MOSFETs

In a power module with multiple MOSFETs connected in parallel, a type of current oscillation known as “parasitic oscillation” can occur during switching. Parasitic oscillation can lead to module failure, so a means of mitigating parasitic oscillation is required. In this paper, we derived oscillation conditions using the Monte Carlo method as well as theoretical analysis of an equivalent circuit, using a simplified circuit model of two chips connected in parallel. Furthermore, we showed that it is possible to apply the oscillation condition to any number of parallel chips by considering them to be equivalent to a two-chip model by performing an appropriate equivalent-circuit transformation. According to these conditions, increasing the value of
$L_{\mathrm{g}}/L_{\mathrm{s}}$
is effective for mitigating parasitic oscillation. To verify the above considerations, we fabricated power modules with different
$L_{\mathrm{g}}/L_{\mathrm{s}}$
values and performed switching measurements. The results revealed that the module with higher
$L_{\mathrm{g}}/L_{\mathrm{s}}$
values mitigated oscillation without increasing switching loss. This novel approach might be useful in designing the wiring structure of power modules.