Influence of Structure Parameters on the RoN, sp of Quasi- Vertical Power DMOS Compatible with 0.18μm BCD Process

Lateral double-diffused MOSFET (LDMOS) is one of the most common devices applied in power electronics fields owing to the favorable high integration. However, the conducting characteristic of an LDMOS is limited, for the existing of the lateral drift region which withstands the blocking voltage (BV). To further reduce the specific ON-state resistance
$(R_{\mathrm{O}\mathrm{N},\mathrm{s}\mathrm{p}})$
, a novel integrated power DMOS with a quasi-vertical shielded gate trench structure (SGT-QVDMOS) compatible to the bipolar-CMOS-DMOS (BCD) process has been proposed. The influence of the crucial structure parameters on the
$R_{\text{ON},\mathrm{s}\mathrm{p}}$
is investigated in details in this work. For an optimized device structure, an ultra-low
$R_{\mathrm{O}\mathrm{N},\mathrm{s}\mathrm{p}}$
breaking the Si limit is achieved.