Highly Optimized High-Voltage SOI p-LDMOS Beating the Conventional SOI Limit

In this paper we demonstrate a novel STI based p-LDMOS that is shown to surpass the conventional SOI (Silicon-on-Insulator) BV (breakdown) limit. Based on TCAD simulations it is revealed that the ultimate breakdown is enhanced due to hole inversion along silicon/BOX (buried oxide) interface which pins the potential. This allows us to utilize the silicon epi thickness to drop the potential from source to drain. It also presents an interesting case to carefully design an optimal SOI architecture.