Experiments of A Novel 3-D Charge Balanced Self-Shielding Isolation Technology for High-Voltage Integrated Circuits

A novel 3-dimensional charge-balanced self-shielding isolation (3-D CSI) technology is proposed and experimentally demonstrated in this paper based on a 0.35 μm bipolar-CMOS-DMOS (BCD) process platform. The 3-D CSI structure is realized by forming internal N-type islands in highly doped P-wells and introducing two deep N-well (DN) regions in the bulk of the device, in which ionized negative charges in the P-well, P-bury, and P-sub regions achieve 3-D charge balance with ionized positive charges in the surrounding DN, N-well, and internal N-well islands regions. The new technology widens the safe operating area (SOA) of the level-shifting Laterally Diffused MOSFET (LDMOS) while increasing the on-state current. In experiments, the breakdown voltage
$V$
B
of the level-shifting LDMOS using 3-D CSI technology was increased from 656 V of the conventional structure to 867 V with a leakage current of just 10
⁻¹¹
A. The 3-D CSI technology has passed 1000 hours of high-temperature reverse bias (HTRB) test and realized the commercial application.