Static Noise Margin Evaluation of Planar CMOS and FinFET based Static Random Access Memory for Nanoscaled Technology

As the semiconductor industry continues to scale down technology nodes to achieve higher density and performance, static random access memory (SRAM) has become an essential component of modern computing systems. SRAM built with conventional planar CMOS transistors faces significant challenges in maintaining stable operation at smaller geometries. CMOS technology has been the mainstream process technology for SRAM design for decades. However, as devices shrink below 20nm, alternative technologies like FinFETs (fin field-effect transistors) are being adopted to continue density scaling while maintaining performance. FinFET transistors provide better electrostatic integrity to enable further scaling by providing higher drive current and lower leakage. This paper analyzes the performance of 6T SRAM bitcell designs using planar CMOS and FinFET technologies at the 16nm node. A standard 6T SRAM bitcell with planar CMOS access transistors was first simulated in Hspice at the 16nm node. Key bitcell performance metrics-read and write margins were extracted. This work analyzes the design and performance of 6T SRAM bit-cells, implemented with 16nm FinFET technology and compares it to 16nm planar CMOS. Results indicate that at 16nm node, the FinFET SRAM cell significantly outperforms planar CMOS in stability margins.