A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations

This brief presents an effective way to design high-throughput and low-power True Random Number Generators (TRNGs) for Field Programmable Gate Array (FPGA)-based digital systems. The proposed design makes an unconventional usage of the Digital Signal Processing (DSP) slice embedded within the AMD-Xilinx FPGA devices to implement high jitter ring oscillators as entropy sources for efficient TRNG designs. Thanks to its wide bit-width output, several configurations can be enabled to group multiple oscillators within a single DSP slice. As a result, a TRNG designed through the proposed scheme outputs up to 4 random bits per clock cycle, thus leading to a considerably high-throughput, while exploiting an ultra-compact architecture. When implemented on the AMD-Xilinx Zynq XC7Z020 System on Chip (SoC), the new architecture achieves a throughput of $800\times 10{^{{6}}}$ bit/sec and an energy consumption of only 22 pJ/bit. When compared to state-of-the-art competitors it achieves a throughput rate up to $2.6\times $ higher and an energy consumption up to $8\times $ lower. The new TRNG has been validated by means of the NIST SP 800-22, the NIST 800 90B and the AIS statistical tests.