Measuring the SoC development process quality with Fault-slip-Through methodology

The System-on-Chip (SoC) development process is needed to manage SoC projects in terms of quality and schedule. At the same time design complexity has grown to a level where it is nearly impossible to get the chip fully bug-free with a single tapeout without re-spins. The design tools have improved in terms of efficiency and can handle more extensive and more complex designs. In contrast, the SoC development process has taken only small steps from a conventional waterfall-based process toward agile development practices. These improvements are important, but so far there are no quantified measurements done to evaluate SoC development process quality. Due to the situation, we present novel results to improve the current state by applying the Fault-Slip-Through (FST) methodology to the SoC development of complex 15 mm
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SoC with multiple subsystems. The FST includes measurements of fault costs, process quality in terms of slipped bugs, and improvement potential of the development process. Our results provide eagerly needed insight into SoC development process quality. The results indicate that FST can be used to evaluate SoC development process quality with certain considerations. With our SoC design and process under evaluation, the results are that 28% of the found bugs slipped through the milestones, but that happened mainly at the beginning of the project. Fault costs due to slips were 340 engineering days of work.