A Capacitor-Less Low-Dropout Regulator with PVT Compensated Adaptive Biasing

This paper proposes a LDO (Low-Dropout) Regula-tor without an output capacitor using PVT (Process, Voltage, and Temperature) Compensated Adaptive Biasing circuit. To improve the current efficiency at the light load, the dual power transistors, and the Adaptive Biasing circuit are used, such that one of the power transistors and the Low-impedance Buffer are turned off at the light load. Besides, the overall bias current is reduced to 0.779 µA to improve the current efficiency at the light load. The proposed design is implemented with a typical 0.18 µm CMOS process. The core area is 474.3 × 730.53 µm
²
. The maximum output current is 20 mA. The peak efficiency of the LDO Regulator is 99.815%, and the current efficiency at the light load of 10 µA is 92.715%.