Design and Simulation of 1 0- Bit SAR ADC Using 18nm FinFET Technology

This paper presents a cutting-edge 1.2V 10-bit asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) meticulously designed and simulated in the advanced 18 nm FinFET CMOS technology. This asynchronous SAR ADC system consists of an internal-clock generator, switching unit, fully differential pair of capacitive Digital-to-Analog Converter (DAC), a dynamic comparator, and a SAR logic. The core achievement of this design is evident when considering its practical performance. Employing a 1024-point Fast Fourier Transform (FFT) on the SAR ADC output and enabling a full-scale input range of 0.96 V differentially. At a rapid 100 MHz sampling frequency, this system attains an Effective Number of Bits (ENOB) of 9.7, showcasing the converter's precision and accuracy. Notably, this achievement is complemented by a Signal-to-Noise and Distortion (SINAD) ratio reaching an impressive 60.17 dB, along with a Signal-to-Noise Ratio (SNR) of 61.25 dB, demonstrating the exceptional signal fidelity captured by the ADC. Moreover, the Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) figures are maintained within a remarkable 1-bit range, highlighting the meticulous attention given to achieving linearity and minimizing errors. This ADC system also drawing a total power consumption of 0.216 mW. This SAR ADC system can be used in systems that mainly require high resolution and high speed.