A Modified Single Tail Dynamic Latch Comparator with pMOS Switches for Low Power Applications

This work reports a novel single tail dynamic latch comparator circuit for reducing static power dissipation without compromising the speed of latch regeneration. Two pMOS control switches are stacked in between the preamplifier and regenerative latch, which is the key element in the proposed circuit. Conventional single tail dynamic latch comparator and proposed single tail dynamic latch comparator with control switches are simulated using 90nm CMOS technology for performance analysis. Compared to other frontend designs, the proposed design is a better option for ADCs in various biomedical applications. From the simulation results, it is observed that the proposed single tail dynamic comparator consumes 38.88 nW of static power with a supply voltage of 1.2 V in comparison with the conventional dynamic comparator with the power of 39.6 nW, which leads to the decrease of overall power consumption. In addition, the proposed design has a total area of 119.4 μm
²
which is less in comparison of conventional with the area of 134 μm
²
.