Radar Emitter Identification based on CNN and FPGA Implementation

Recently, deep learning (DL) models based on convolutional neural networks (CNN) have been used for radar emitter identification (REI). However, CNNs typically have high parameter and computational complexity, posing a challenge to limited computing resources in FPGAs during deployment. In view of this, we propose a lightweight model based on deep separable convolution, and use iterative pruning, parameter quantization to further reduce model complexity. Finally, we use various computational optimization methods to reduce hardware inference latency. The proposed scheme can achieve a real-time throughput of 113.6k frames per second for radar emitter signals obtained through IQ sampling at a 250MHz clock frequency on AMD RFSoC platform. At the same time, it can maintain a classification accuracy of over 90% under a signal-to-noise ratio of -8dB.