Area Efficient R adix-2k R econfigurable SF F Pipeline FFT Using Constant Multiplier

This paper presents a serial pipeline FFT circuit that employs a processing unit with a single-path FPGA-optimized feedforward (SFF) structure and a constant multiplier rotator for the R-2
^k
FFT algorithm. It further achieves the length-reconfigurable feature of the FFT circuit through the use of multiplexers and rotator control. Addressing the issue of resource consumption in the processing units of FFT circuits, this study introduces SFF processing units into the previously established single-path delay feedback (SDF) pipeline structure. This approach provides an effective method of reducing the number of complex adders by opting for a higher consumption of short shift registers. By exchanging resources between short shift registers and adders, an overall optimization is achieved, leading to a reduction in the resource consumption of the circuit’s processing units. Regarding the consumption issue of Rotators in FFT circuits, this paper introduces a binary tree-based FFT decomposition method to obtain an optimal distribution of Rotators. By converting some Rotators into a form that can be implemented through Constant Multipliers, the multiplication resource consumption of the structure is reduced. Finally, through theoretical analysis and comparative experiments on FPGA, the resource consumption advantages of the proposed structure are demonstrated.