Unveiling the Potential of 12T SRAM for Enhanced Performance and Efficiency

Unveiling the Potential of 12T SRAM for Enhanced Performance and Efficiency stands at the forefront of innovation, addressing the critical need for reliable and energy-efficient memory solutions in low-power applications. The goal of the research is to properly read and write the suggested cell while lowering the total power dissipation and latency. To investigate and assess the performance characteristics of Static Random Access Memory (SRAM), we used the simulation programmes LTSPICE and HSPICE. Drawing inspiration from recent advancements in SRAM design, our research introduces a specialized architecture while maintaining low power consumption. Leveraging subthreshold operation, the proposed design ensures high stability and reliability crucial for storing critical biomedical image data, performing logic and arithmetic in-memory operations.Through comparative analysis with existing SRAM cell designs, including conventional 6T SRAM, A Reliable Low Expanded Static 10T SRAM Cell for Standby Power Noise Margins, EDP12T SRAM, our proposed SRAM architecture demonstrates superior performance. These include reduced delay, lower leakage power dissipation, and improved area efficiency, making it an ideal choice for a wide range of low-power applications.