Implementing Energy Efficient Circuits Using Negative Capacitance Field Effect Transistors

This project delves into the characterization of Negative Capacitance Field-Effect Transistors (NC-FETs) to assess their viability in optimizing energy efficiency within digital circuits. Through comprehensive analysis, including simulations and experimental validation, the study aims to quantify the efficacy of NC-FETs in minimizing power consumption and enhancing energy efficiency in fundamental digital building blocks such as inverters, half adder, and full adder, leveraging their unique characteristics. Additionally, the investigation extends to the implementation of a 4-bit Vedic multiplier using a carry-save adder, following the Urdhva-Tiryagbhyam sutra, chosen for its parallelism and suitability for low-power applications. By integrating NC-FETs into the Vedic multiplier design and contrasting its performance with conventional CMOS architectures, this project seeks to elucidate the potential of NC-FET technology in drastically reducing power consumption while maintaining computational efficacy, thereby advancing the landscape of energy-efficient digital computing paradigms