High Speed 64 Bit Vedic & Booth Multiplier Implementation Using FPGA

This work aims to showcase the significance of Vedic and Booth mathematics in the realm of Computer Applications. Good precision, speed, area reduction, and low power consumption are primary features of a multiplier. Multiplication operations require speed and speed can be enhanced by decreasing the number of steps needed to complete the computation. The requirement for high-speed operations in digital devices has become a primary need nowadays. This research delves into two distinct multiplier algorithms–- namely, the Vedic Multiplication Algorithm and the Booth Multiplication Algorithm–-conducting an extensive exploration to determine through comparison which multiplier demonstrates superior performance across various metrics such as delay, power, and other commonly utilized performance indicators. While the Booth Algorithm involves a reduction in partial products, the Vedic Multiplication Algorithm is built on Urdhva Triyakbhyam sutra of Vedic Mathematics. The complete design, simulation, and synthesis procedures were executed through Xilinx Vivado, utilizing Verilog as the Hardware Description Language (HDL). The hardware implementation was conducted on an FPGA (Field Programmable Gate Array).