Enhanced 11-Transistor SRAM Cell with Half Select Disturb-Free Operation for High Performance Systems

abstract-A unique 11T Static Random Access Memory cell is designed intended to extremely low voltage applications, ensuring immunity to half-select disturbance issues. Because of its integrated write/read-assist approach, both of the Write/Read static noise margin are greatly enhanced. The simulation results using a 7nm standard FINFET Technology, show that the Read Static Noise Margin (RSNM) of the (11T) SRAM Cell is improved by 10.6% and 19.2% compared to 10T and 6T SRAM cells. It also attains a proportionally greater Write Static Noise Margin (WSNM) with the designed 11T SRAM cell. Consequently, a reduced minimum operating voltage is attained. Its leakage power is also decreased by 67.05% and 35.15% relative to 6T, 10T SRAM Cell.