Electro-Thermal Cosimulation of Vertical One-Transistor–One-Resistor (1T1R) Resistive Random Access Memory and Array

With switching dynamics similar to synapses, resistive random access memories (RRAMs) provide the solutions for brain-inspired computing. In this article, a compact model for a vertically integrated one-transistor-one-resistor (1T1R) element is developed, which includes an equivalent electrical circuit (EEC) and equivalent thermal circuit (ETC) model. The accuracy of our model is verified by comparisons with experiment data and numerical simulations. The electro-thermal co-simulations of the 1T1R cell and array are performed by using the compact model to capture both the steady and transient electro-thermal response of the device. Furthermore, the thermal crosstalk effect in a
$4\times 4~1$
T1R array is discussed by comparing the electro-thermal simulation results of the memristor cell in different write operating modes, which indicates that the thermal crosstalk during parallel write operating mode may cause the timing errors of RRAM circuits. Finally, the influence of background temperature variation on the resistive switching characteristics of the device is studied.