Design of a 32-bit Datapath for a Reduced Instruction Set Computers (RISC) Implementation using the DE0-nano FPGA

The design of a 32-bit datapath allows computer architect to simulate possible extents for RISC based processors to other form of operations needed for complex applications. The study aims to analyse the device accuracy and its functionality such that Application Specific-FPGA (AS-FPGA) can be constructed for future use or applications and become part of a fully functional device. In order to have a fully functional datapath and control unit, the operations intended for such application must have an accurate data value to be used in the data processing; instructions in the arithmetic and logic operations, flag bits, memory, and register files that are directed by the control unit and is controlled using code bit as part of the machine code. The design must have functional units such as the control unit, program counter, instruction memory, register file, sign extender module, multiplexers, arithmetic logic unit (ALU), and the data memory. The study was successfully designed a 32-bit single-cycle datapath and simulate RISC based instructions in XILINX-ISE and successfully implemented the design in the DE0-nano FPGA targeting the Cyclone-IV FPGA. The testing for accuracy and functionality with the two approach resulted to an overall success rate which means that both approach in the simulation and implementation correspond with the same output.