Implementation of High Speed and Low Area Novel 16-Bit Vedic Mathematic Algorithm Using Sklansky Adder in Comparison with Carry Select Adder

This research contrasts the quick speed and low area performance of a special Sklansky adder with a carrying select adder in a 16-bit Vedic multiplier. Materials and Procedures: This paper compares the performance of a cutting-edge 16-bit Sklansky adder-based Vedic multiplier with a standard Carry select adder (CSLA) Vedic multiplier. Modelsim was used to replicate the Vedic multiplication algorithm, which was built in VHDL. Time and area analyses of the simulation findings were conducted, and the outcomes were contrasted with those of a traditional Vedic multiplier built on a Carry Select Adder. Two sets of ten simulations each were used to assess the productivity for the Carry Selective Addition for 16-bit Vedic multipliers utilizing the Sklansky adder. The area was calculated using the number of gates and the physical dimensions needed for implementation; the delay was calculated using the time interval between changes in the productive input and changes in the productive output. The suggested design was developed using alpha and beta values of 0.05 & 0.20, respectively, using the G-power technique. Together with the advantages and disadvantages of each choice, the findings included a 95% confidence interval. According to the data, the Sklansky adder had a delay time of 12.1 ns, whereas the carry select adder has a delay time of 16.2 ns. Additionally, the Sklansky adder has 934 LUTs, a larger area than the carry choice adder's 635 LUTs. At the p-value, the research's significant value was found to be 0.000 (P < 0.05). The research study's findings indicate that the Sklansky adder, which is smaller and has a shorter delay time than the carry select adder, is a superior choice for high-speed digital signal processing applications. This investigation may provide insights into the construction of Vedic multipliers and other high-speed arithmetic devices.