Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact

Scan design adversely affects design performance, including speed, power, and routing congestion. Scan partitioning and reordering are required to mitigate these effects. We present an unsupervised machine learning-based method for scan partitioning to reduce the total scan wire length and make scan chains as compact as possible. For scan partitioning, we use the K-Means clustering method and reorder flops in a scan chain using the Traveling Salesman Problem (TSP) algorithm. Experimental results for three CPU designs show that significant savings in real wire length (2-3%), as well as a reduction in timing impact (27%), can be achieved with the proposed method compared to the best case obtained by a commercial EDA flow. Additionally, the optimized scan stitching also helped improve Design Rule check (DRC) violations, which aids in design closure.