Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling

The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. We aim to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on two example circuits, a flash ADC and a PLL, show that accurate simulations can be achieved at a fraction of the simulation time.