A Face-to-Face Layout of Silicon Carbide Power Module Co-Designed Considering Electro-Thermal Properties

The superior performance of SiC MOSFETs is accompanied by the challenges of designing for low parasitic inductance and strong heat dissipation capacity. In this paper, a double-sided cooling module with a face-to-face layout is proposed, which has lower parasitic inductance and better thermal performance. ANSYS Q3D simulation results show that the parasitic inductance of power loop without power terminals is reduced to 1.94nH by using vertical interconnects in a unique 3D layout. The power loop parasitic inductance is 4.4nH when unoptimized power terminals are included, which is verified by experiments. Also, thermal simulations show excellent heat dissipation for the proposed power module. The junction to case thermal resistance is only 0.11°C/W.