Software Implementation of Fast List Decoder for PAC Codes

In this letter, a novel high throughput software polarization-adjusted convolutional (PAC) decoder based on the four-node fast list (FFL) decoding algorithm is proposed. To improve the parallel processing capabilities of the proposed decoder, we effectively parallel map the FFL decoding algorithm to processors by using the single instruction multiple data (SIMD) instruction set to decode multiple frames of data in parallel. Moreover, the proposed decoder has sufficient generality to be implemented on X86 and ARM processors (NEON, SSE, and AVX256 instruction sets). Experimentations show that the proposed software PAC decoder can achieve 26.256 Mbps.