Reliability Assessment of Stacked-Vias with Different Configurations through a Unit Cell-based Substrate Design

There is an increased need for having stacked-via structures within organic substrates used in microelectronic packages to meet the requirement for higher throughput for a given package footprint. Reliability of these structures when exposed to temperature excursions has been a cause of concern. Considering that there are several geometrical, spatial, and material factors that could interact and determine the failure rate of these structures, there is a need for a time and cost-effective way to understand and quantify its reliability as a function of all the anticipated dependent factors to enable subsequent robust design and introduction into product hardware.In this work, a unique unit cell-based test substrate was designed with over hundred different geometrical and spatial combinations of stacked-via structures. Single chip module test vehicles were built using these substrates fabricated with one of the three dielectric build-up materials with different set of material properties. These modules were thermal cycled and electrically tested to quantify the failure rate dependencies with all the design factors. Our work indicated that the number of vias in the stack, via diameter, the in-plane and out-of-plane placement of these stacked vias within the substrate, proximity to other design features within the core, number and type of via-jogs and material properties of the surrounding dielectric material play an important role in determining the failure rate of these structures. This work was done using just one laminate design and all the failure rate dependencies were obtained using just electrical probing alone without the need for having to do any destructive failure analysis thereby saving immensely on both time and cost.