Advanced FO-PLP with Multi-chip for Wearable Application

It has been investigated the core technologies for fan-out panel-level package (FO-PLP) using multi-chip in wearable application. For thin and small form-factors, FOPLP with embedded multi-chip and high density memory were stacked as package-on-package (PoP). Recently, we are facing new challenges with asymmetric multi-chip structure. Because the wearable devices are being developed in various forms, the demand is increasing for integrating multi-chips with various sizes into a single package to minimize the package form factor. However, each chip is changing in size according to its functionality and the various purpose. Integrating multi-chips into a single package, it results in the increased asymmetric design with high aspect ratio. Those asymmetric structure and high aspect ratio would be led to high risk for warpage and reliability. Therefore, we focused on the warpage control with effective gap analysis and vertical stack-up optimization, and the reliability of package-level was characterized in JEDEC conditions, respectively.In this paper, we reviewed the optimized structure through simulation and found the solution by increasing die thickness to meet warpage control and reliability specification in asymmetric structure. As a result, the warpage of package was achieved less than 40um while the package total height was remained the same with stable process capability. Moreover, package-level reliability (PLR) result was passed under JEDEC TC-B (-45~125℃) criteria. Through this evaluation, the core technologies of FO-PLP can be implemented to products using multi-chip for wearable application.