Single and Multi NPU Chiplet Heterogeneous Integration packaging based on Fanout RDL interposer with Silicon bridge technology

A chiplet is a die that is designed to be integrated with other chiplets in some type of advanced package. That package could be a system-in-package (SiP), 2.5D (planar or vertical), or 3D-IC. Nearly all chiplets in use today are being developed with some sort of standard interconnect or protocol and re-use them across multiple designs. Logic, memory, sensors, MEMS, mixed-signal, or any one of a variety of different functions can be developed as chiplets. And a 28nm chiplet may be placed next to, and work together with, a 5nm chiplet. The concept is basically to shrink a printed circuit board and put all the pieces into a much smaller space. That increasingly exceeds the size of a reticle, which 858mm² with EUV steppers, and 429mm² with high-NA EUV steppers.nepes has been developing NPU (Neuromophic Processor Unit) to be integrated together with memory(HBM) or other chiplets by 2.5D Heterogeneous Integration technology. 2.5D Heterogeneous Integration package includes Fan-out based on RDL interposer. Two types of 2.5D package were considered according to the applications, like edge computing or data center computing, kind of more complicated application. The application of edge computing would be less performance compared to the application of data center computing. Then, its NPU needs to be interconnected with memory (HBM or DDR) directly while multi NPUs need to be integrated with memories by embedded bridge technology inside RDL interposer. In case of multi NPUs packaging with memories, Silicon bridges need to be embedded inside RDL interposer as a signal interconnection between NPU and memory or between NPU and NPU.Firstly, single NPU packaging with memory has been developed by applying RDL interposer technology in terms of edge computing application. Single NPU was integrated with two HBM3 on an RDL organic interposer which consists of multi RDL layers (over 6 layers without UBM and pad layer) with minimum line and space of 2 um. In order to interconnect between NPU and two memories (HBM3) directly without any bridge, six layers of RDL were developed with fine pitch RDL line/space of 5/5 um, 3/3 um as well as 2/2 um. The smallest CD of dielectric material which is less than 10 um was developed and setup to be able to form multi fine-pitch RDL layers. The process of flip-chip bonding of NPU & memories onto the RDL interposer was developed.Secondly, multi NPU Chiplets packaging technology needs ultra-high-performance AI semiconductor architecture design and RDL interposer structure development reflecting heat analysis and performance optimization simulation and the development of AI semiconductors with heterogeneous integration of more than 10 chiplets with optimized heat dissipation and performance. In order to get the optimized architecture in terms of heat dissipation and performance, related simulations have been under development. Concurrently, 2.5D system-in-package architecture and process flow development have been under development for the development of high density RDL interposer element technology with bottom side RDL process technology (Multi-layer, Fine-pitch RDL layer) and high A/R (1:2) Cu-post process technology. On top of that, the development of bridge die embedding process technology has been undertaken with fine pitch Cu stud bump technology, thin die (<100um) handling process as well as high-precision (±5um) die bonding technology and encapsulation and co-grinding (EMC/Cu) process technology.