Signal & Power Integrity Optimization Utilizing Silicon Core Substrate

Advancements in IC package interconnect technology has enabled heterogenous integration (HI) of various technology nodes with high-bandwidth 2.5D and 3D interconnects, e.g., HBMx, UCIe, USR etc. High Bandwidth connections are typically limited to horizontal connections. The vertical component of the interconnect from chip to PCB is still relatively poor due to limiting organic core substrate design rules. Thus, limiting overall signal & power integrity (SIPI) performance of package interconnects.As the package grows in lateral dimensions the organic core is typically required to be substantially thicker, e.g., 0.8mm-1.2mm, to mitigate unwanted mechanical stresses, e.g., warpage/deformation, inherent with larger and more complex HI packages. Silicon Core Substrates on the other hand facilitate up to an order of magnitude reduction in package thickness, while simultaneously mitigating package warpage with optimized package to device silicon CTE match.In this white paper we quantify the key SIPI performance advantages of Silicon Core Substrate technology vs. traditional organic core substrate packages. The power-distribution-network (PDN) has significantly less loop-inductance allowing for larger delta-I operation while meeting increasingly stringent voltage noise requirements. Series resistance is reduced for optimal DCIR performance. Multi-Gigabit SERDES IO benefit from improved insertion loss allowing higher Nyquist frequencies and off-package IO bandwidth. Inherent and unwanted higher-order-mode-propagation, e.g., ½ wave resonances due to package core thickness found in typical organic packages, are mitigated with silicon core substrates allowing higher fundamental frequencies to propagate via the off-package interconnects with optimal SI and EMI performance.