Package Miniaturization and Wiring Impedance Reduction for High-bandwidth Memory Devices with Vertical Wire Bonding

The demand for high-speed signal transmission within packages is increasing due to the increasing interface bandwidth of memory dies. To satisfy this demand, an effective approach is to reduce, in signal transmission paths, the parasitic capacitance and parasitic resistance that cause signal distortion and delay. The parasitic capacitance of transmission paths in a package is largely dominated by the pad capacitance of dies. In the case of NAND flash memory packages, another factor needs to be addressed, namely, the trade-off between having multiple dies and reducing package size. Therefore, pads of multiple dies are connected in parallel inside a package. To overcome these limitations of such conventional packages, a new package structure is proposed. Vertical wire (VW) bonding technology can contribute to simultaneously reducing parasitic capacitance, parasitic resistance, and package size. A daisy-chain test samples was fabricated to assess the reliability of the proposed package. After optimizing the fabrication processes, all daisy-chain test structures in a package passed electrical tests. Reliability tests were also conducted. These results suggest that the die-to-VW and VW-to-solder bump connections by VW bonding technology have sufficient robustness, and the proposed package structures have the necessary reliability.