Overlay Challenges of Extremely Large Exposure Field, Fine Resolution Lithography Due to Alignment Solution Errors and a Solution Using Early Zone Corrections in Advanced IC Substrates

There is no doubt that the artificial intelligence (Allpowered ChatGPT is one of the year’s most popular Al technologies. However, Al will require chiplet technology to continue to meet the stringent specifications of current and future Al innovations like ChatGPT. And the key to enabling chiplets is advanced packaging. Ultra-high density (UHD) fanout packaging and 2.5D/3D packaging are two such advanced packaging technologies that people are proposing for the manufacturing of chiplets. To achieve the requirements of these advanced packaging technologies, a large packaging area, smaller line/space and finer ball pitch requirements, and an increasing number of layers will need to be implemented in the manufacturing of advanced IC substrates (AICS).Extremely large exposure field, fine resolution lithography is one of the keys to enabling these requirements in AICS. An extremely large exposure field enables the exposure of large packaging areas without stitching, while the technology’s fine resolution capabilities enable small line/space and finer ball pitch requirements. But even though extremely large exposure field, fine resolution lithography has many advantages, it faces several challenges. One of these is a tight overlay budget resulting from the increasing number of layers and finer redistribution layer (RDL) pitches. Alignment solution errors are one of the major factors that result in overlay errors and induce low overlay yield. To address these alignment solution errors, early zone correction technology is proposed. In regard to panel overlay, this early zone correction technique utilizes an algorithm to analyze the correctable components on a per zone basis and then uses these zone based corrections during the lithography process to address the influence of alignment solution errors, resulting in improved overlay.