Fusing Current Characterization of Various Cu RDL Designs in Wafer Level Packages

The demand for high current is constantly increasing with the increased requirements for high-power in automotive, artificial intelligence (AI), networks, wireless charging applications, etc. This increasing the high current demand is required for the wires in low frequency (LF) products and also for redistribution layer (RDL) interconnections in Wafer Level Packages (WLPs). The existing theoretical equation for fusing current is very limited since it only considers material types. Consequently, fusing current characterization is needed for the various RDL designs and structures of WLPs.In this study, the fusing current of the copper (Cu) RDL was evaluated with various RDL designs, patterns, silicon (Si)-die thickness and Wafer Level Packages. The resistance of Cu RDL was measured by four-point measurement techniques and the current was provided by a source measure unit (SMU).This paper discusses the fusing current of RDLs as a function of heat dissipation behavior depending on the package structures as well as RDL designs. A thermal simulation model was also developed and validated with actual fusing performance so that it can predict fusing performance for different RDL designs and different package structures.