Key Technologies and Design Aspects for Wafer Level Packaging of High Performance Computing Modules

As contribution to projects like European Processor Initiative (EPI) as well as Stencil- and Tensor Accelerator (STX), Fraunhofer IZM has further developed its advanced packaging portfolio with special focus on wafer level packaging of high performance computing (HPC) modules. This includes the further scaling of the well-established multi-layer copper redistribution technology to enable a 4 μm line / space routing (8 μm pitch) over multiple layers with 6 μm thick polymer interlayer dielectric and micro vias of 8 μm diameter. The redistribution layers (RDL) provide the signal routing on top of a TSV interposer device and related RF simulations show the capability for a very high signal integrity and low transmission loss of this routing scheme to be more performant than inorganic routing schemes based on SiO dielectric and copper or aluminum metallization. The RDL technology is based on semi-additive copper structuring and excimer laser ablation for generation of the micro vias. It is further scalable down to 3 μm line / space (6 μm pitch) and beyond.Further key elements of the WLP flow for the fabrication of HPC modules are TSV interposer processing including front side RDL and back side pad formation followed by flip chip assembly, underfilling, compression molding and a final back side balling of the TSV interposer device.As one example of fabricated HPC modules we present Occamy, which is a 2.5D integrated dual-chiplet system designed by ETH Zürich and supported by the Europractice-IC team at Fraunhofer IIS. The system contains 2 compute chiplets fabricated in GlobalFoundries 12 nm FinFet technology as well as 2 high bandwidth memories 2e (HBM2e). Each compute chiplet has a size of 73 mm
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and includes six groups of four compute clusters, the host CVA6, an HBM2e controller IP from Rambus, as well as a source synchronous serial DDR die-to-die link. All 4 ICs are mounted on a passive 600 mm
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silicon interposer called Hedwig which is fabricated in GlobalFoundries 65 nm technology. Related packaging work performed at Fraunhofer IZM was interposer TSV back side reveal, front and back side pad formation, flip chip assembly, underfilling, balling and second level assembly to PCB. Further details will be presented in this paper.