Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration

This paper presents a ground-signal-ground (GSG) interleaved high speed interconnect transmission lines (T-lines) configuration, implemented for high bandwidth memory (HBM3) 2.5D-IC interconnection, through TSMC CoWoS-R® organic interposer technology. In 2.5D-IC chiplets integration, signal integrity (SI) design-optimization at the high speed interconnects also plays a critical role. This SI design-optimization needs to consider chip-to-chip interconnects’ post-layout parasitics for high speed transmission capability, especially, while data rate up to 9.2 Gbps/lane. Typically, interconnects’ parasitics, e.g., insertion losses and crosstalk, are the dominant factors to signal integrity. To overcome the impacts of interconnects’ parasitics and achieve 9.2Gbps/lane data transmission, the proposed GSG-interleaved T-lines configuration shows its benefits at lightly fan-outs capacitance, low insertion losses, low crosstalk, and high routing density, where this interconnects’ insertion loss can be suppressed to 0.38dB/mm, and near-end crosstalk to -37.6dB at 4.6GHz. With the aid of this proposed GSG-interleaved T-lines, this work successfully demonstrates HBM3 data transmissionoperating at 7.2Gbps/lane and 8.6Gbps/lane by two silicon testchips. The first testchip in TSMC 7nm technology is measured with eyewidth more than 0.560UI at 7.2Gbps/lane, and the second silicon testchip in TSMC 3nm is measured with 0.48UI at 8.6Gbps/lane. As well as co-simulated eyewidth can also achieve 0.595UI at 9.2Gbps/lane for good signal integrity performance.