World’s First UCIe Interoperability Silicon Enabling Open Standards Heterogeneous Integration

Heterogeneous chiplet integration has been a major focus in recent chip design architectural choices. It provides a method to design different functionality onto the most optimal process technology nodes, while bringing these different chiplets into a single package improving system performance and reducing overall cost. The Universal Chiplet Interconnect Express (UCIe) standardization of the die-to-die interface allows for the flexibility of mixed-foundry integration. The team has demonstrated the world’s first UCIe interoperability silicon demonstration using 2
^nd
generation 2.5D Embedded Multi-die Interconnect Bridge (EMIB) advanced package technology. The demonstration comprises of mixed Intellectual Property (IP) vendor designs on mixed foundry silicon showing open standards chiplet ecosystem readiness on IP, package and foundry technologies. This presentation will provide insights into the importance of die-to-die interface standardization and ecosystem readiness. We will also highlight some key results along with challenges and learnings during the test chip development. This UCIe interoperability is an important milestone for an open standards chiplet ecosystem for heterogeneous integration designs.