Study of Damage Development in Under-Bump Interconnects by Thermo-Mechanical Stress in Package Interconnects

This paper reports a study of damage development in the under-bump back-end-of-line (BEOL) interconnects instigated by a thermo-mechanical Si-chip and package interaction (SPI). Specifically, this paper addresses more on the method of detecting such damages to meet the growing non-destructive fast characterization methods in the field. This technique relies on an impedance measurement at low frequency with varying magnitudes of AC voltage on interconnect patterns designed to produce signals sensitive to the presence of damage and its location. Samples developed for the technique were composed of solder bumps and a Si chip with two-layer Al spiral patterns and vias included in the circuit. Creating varying levels of inductance, the resulting impedance response to AC signals consisted of multiple humps in the phase angle/inductance components due to the presence of the multiple interconnect spiral patterns on the BEOL interconnects underneath the solder bump. When the same pattern was characterized after subjecting it to damage inducing temperature cycling, a significant change in the phase angle was seen at the resonant frequency of a spiral where damage was located. The change appeared as a step increase (or a singularity in resonance) in the inductance and phase angle, and the change became more pronounced with the increase in magnitude of the AC signal. An analysis indicates that the hump was due to LCR resonance and the steps in inductance/resistance component was related to the development of a current leakage path in the SiO
2
dielectric layer. Utilizing this technique, various tests were conducted to study the damage mechanisms. The study revealed that a location exists in the under-bump interconnects that is more prone to SPI damage. In addition, it was also discovered that certain locations in the chip (edge, middle, etc.) had a significant effect on the damage kinetics. In this paper, experimental findings, a potential stress interaction between the solder bump and under-bump interconnects, and an equivalent circuit analysis to assist failure analysis without using microscopic inspection is presented.