Thermal Mitigation Strategy for Backside Power Delivery Network

By improving power delivery capability and mitigating signal routing congestion, Back Side Power Delivery Network (BSPDN) has been proven to be a game changer for the next generation of chip design. However, it also brings thermal challenges due to a significantly larger thermal resistance between the CPU power grid and on-chip forced cooling. Therefore, a cutting-edge cooling scheme is needed to tackle this issue. Inspired by the similarity between Back End of Line (BEOL) layer structure and 3D manifolded microchannel cooler, we propose an innovative embedded microchannel cooling configuration to bring the coolant closer to FEOL, which also cooperates with chip-top jet cooling to form a dual-sided cooling system. Finite Element Analysis (FEA) is performed to study the thermal performance of chips and cooling effectiveness and efficiency for microchannel cooling. Due to the high complexity of a detailed BSPDN model, several engineering approaches are utilized to reduce the computing resource requirement. Detailed Back End of Line (BEOL) thermal models are established and investigated for computing its accurate orthotropic thermal conductivity. Then, a local unit cell model including both BSPDN chip and coolant region are simulated through system coupling approach, after which the effective Heat Transfer Coefficients (HTC) are extracted and applied to a 50 μm × 50 μm overall model with power map heat source. A control parameter study is conducted by varying coolant type of water and air, inlet flow velocity, and inlet flow temperature. It turns out that the microchannel cooling with 283K, 0.06m/s water inlet can reduce the maximum temperature by more than 20% or about 20°C for both uniform heat flux and heat map cases, at an expense of 2581 Pa inlet pressure.