Cu/Dielectric hybrid bonding among Glass and Si

Chaplets and advanced packaging technologies play a pivotal role in meeting the diverse and demanding requirements of data-intensive workloads, by offering solutions that encompass performance, power efficiency, form factor, and cost-effectiveness. These package architectures demand a higher interconnect density among chiplet’s to package substrate. Conventional organic and ceramic substrates are more apparent in scaling the electrical wire, due to signal integrity, radiality, and manufacturing challenges. Glass substrates are becoming a prominent replacement for conventional package substrates due to their high thermal, and mechanical stability with ultra-low surface flatness. In this endeavor, a fine-pitch (~6 μm) Cu/dielectric hybrid bonding process among glass to silicon substrates has been demonstrated at a low temperature of ~⩽ 250 ° C, with N
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plasma treatment. The detailed investigation of the selection of glass substrates and challenges associated with processing it in the process line. The surface inspection resulted in an oxide surface roughness to be <0.3nm and Cu dishing controlled to < 5nm on both glass and silicon wafers fabricated with optimized process control. Furthermore, 90% void-free bonding was observed using interface acoustic imaging (C-SAM) and Cu-Cu grain growth was observed by cross-sectional FIB-SEM inspection. These investigations are expected to benefit future trends in advanced packaging with glass substrates.