How to Manipulate Warpage in Fan-out Wafer and Panel Level Packaging

Fan-out Wafer and Panel Level Packaging are two of the latest trends in microelectronics packaging. Both approaches come with different flavors as RDL last and RDL first and have reached maturity and are introduced in high volume manufacturing. Clear application trends and technology roadmaps do exist. This ranges from low density core technology for e.g. RF or PMIC (power management IC) packaging over high density application processor packaging to ultra-high density applications for networking servers etc..One key challenge during fan-out wafer and panel manufacturing is warpage. Warpage is mainly caused by the CTE differences of the process carrier, epoxy molding compound (EMC) and the embedded dies and the chemical shrinkage of epoxy mold during curing. Besides the material properties also the geometries have a significant influence on the resulting warpage. This includes carrier thickness and stiffness, mold thickness, die thickness and overall silicon content but also the lateral wafer/panel dimensions. Warpage will change with each process step - also during subsequent RDL application. Hence, the goal is not to minimize the warpage at a certain process step but to keep it controlled through the entire process to ensure a reliable processing. Besides the absolute size of the warpage also shape and finally the stiffness of the panel contribute significantly to the manageability of panels during processing. This makes it also difficult to define warpage limits for handling and processing.Deeper understanding of influencing material and process parameters are necessary to forecast and manipulate the warpage behavior during processing. Several design of experiments (DOE) have been performed to study and evaluate different factors as mold thickness, die thickness or silicon density. Results clearly show the impact on warpage but also missing factors based on the confident level of the results. A special compression mold tool has been designed and installed to further study the influencing factors of the mold embedding process. The focus here is process homogeneity in flowing and curing as well as the effective cure shrinkage. Finally, strategies for manipulating the warpage have been developed. It was found that uniformity of area population of dies is advantageous and thus the assembly of e.g. dummy dies within the handling frame of the wafer/panel significantly reduces warpage. In addition, introducing warpage adjust steps by keeping the wafer/panel on a vacuum stage for a certain time and temperature during e.g. cooling from debonding or other temperature treatments can also reduce the warpage.In summary experimental studies are shown for deeper understanding but also for manipulating the warpage during fan-out wafer and panel level packaging.