High-Performance Thermal and Electrical Characteristics of Via-Last (BBCube) Process in Multi-Layer 3D Integration

Multi-layer 3D integration is receiving attention in AI and HPC applications, which demand wide bandwidth and high power efficiency. Micro-bumps have conventionally been used for stacking, while bumpless 3D integration has been proposed to increase connection density and the number of stacked layers. There are two methods for vertical connections in bumpless integration: via-first and via-last. In the via-first process, TSVs are formed in advance, and Cu of TSV is exposed from the backside of the wafer using thinning and nm-level planarization processes. After stacking wafers, annealing is used to form a conductive interface between Cu pads on the upper and lower dies. In contrast, in the via-last process, the upper and lower dies are connected using a similar method to multilevel metallization in the back-end of line (BEOL) after stacking the wafer or chip. The differences in the processes impose different limitations on the TSV pitch, bonding layer thickness and Si substrate thickness. However, the impact of these differences on the thermal and electrical characteristics is not well understood. Hence, we created detailed models of the TSV area and circuit area, and performed thermal analysis and electromagnetic field analysis on each. According to the analysis results, the via-last process can reduce thermal resistance to 13% in the TSV area and to 42% in the circuit area compared to the via-first process, and via-last process can also reduce parasitic capacitance of TSV to 29%. These results indicate that the via-last process can provide advantages in terms of both the electrical and thermal characteristics in multi-layer 3D integration.