Zero-misalignment Technology Achieves 333 IO/mm/layer on Mold

Integrating redistribution layers (RDLs) directly on epoxy molded compound (EMC) surfaces, provides a valuable building block for technologies like Omni-Directional Interconnect (ODI) and Quasi-Monolithic Chips (QMC). Additionally, the fundamental learnings of this building block and its applications are directly applicable to other technologies such as hybrid bonding or Photonics; technologies which are part of Intel’s wafer level packaging heterogenous integration schemes for 2.5D and 3D packaging that are needed to extend Moore’s law. In this report, Zero-misalignment via (ZMV) technology is leveraged to enable RDL on mold; a pattern anywhere and everywhere lithography technology that is used here to build a dual stack redistribution layer (RDL) directly on mold. The result is an intrinsic fully aligned via and pad combination, that removes the need for two lithography steps within a single layer, one for trace and one for via definition. ZMV, in combination with a non-selective chemical mechanical polish (CMP) process is a viable method to improve performance at reduced and processing cost. Here we demonstrate early efforts on patterning of 333 IO/mm/ly over molded Cu pillars with a 0.1 μm Root Mean Square (Rq) roughness.