Interfacial Reliability and Predictive Models for Potted Board Assemblies in Inclined 25000 g Mechanical Shock

Electronics used in military defense applications increasingly rely on the use of commercial off-the-shelf electronics. Extreme environment applications expose the electronics to high temperatures in addition to high g acceleration loads during transportation, storage, or handling. Reliability expectations in mission-critical applications necessitate the understanding of survivability, failure mechanisms, and efficacy of supplemental restraints such as potting materials in mitigating the propensity for failure. Interfacial damage thresholds needed for predictive modeling or the effect of sustained high temperatures on the propensity for interfacial potting failure are largely absent in the state of the art. The research objectives of this study include the measurement of potting material interfacial fracture toughness after sustained exposure to high temperature for periods of up to 1 year, the effect of mode mixity using CNF and ENF measurements, and the development and validation of high-g mechanical shock models. The potting/PCB interfaces have been exposed to high-temperature exposures at 100°C and 150°C. A circular printed circuit board assembled with fine-pitch electronic packages and multilayer ceramic chip capacitors has been potted and tested under high G shock loads. The fracture toughness parameters have been used to calculate the cohesive zone parameters at the interface. The effect of shock orientation on the failure propensity under 30-degree and 60-degree shock orientation has been examined. A predictive model has been developed for the assessment of interface and interconnect failure. The model has been validated with experimental data acquired from high-speed imaging in conjunction with digital image correlation for measurement of out-of-plane deformation and strains.