Thermo-Mechanical Reliability Analysis and Raman Spectroscopy Characterization of Sub-micron Through Silicon Vias (TSVs) for Backside Power Delivery in 3D Interconnects

This study focuses on the fabrication and thermomechanical characterization of Through Silicon Vias (TSV) with diameters spanning 1-4 µm. In terms of TSV fabrication, scallop-free Si etching is achieved by the optimization of the Bosch etching process, and a void-free TSV filling is completed by a combination of electroless plating for seed layer and electroplating for TSV Cu filler. After that, the thermomechanical response of TSVs is stress-imaged via Raman spectroscopy. Thermal stress is developed in the Si after an annealing process at 400°C, which is attributed to the shrinkage of the Cu core as the sample cools down from the annealing temperature to room temperature. The stress profiles of TSVs with different diameters are measured and compared, revealing an equivalent stress level consistently below 100 MPa for all diameters. This lower stress level is attributed to the offset between tensile radial stress and compressive tangential stress. With the pitch fixed for different-sized TSVs, the interaction between adjacent TSVs is reduced for smaller TSVs, leading to a lower stress level and a transformation from single-peak to dual-peak stress distribution.