Design Space Exploration for Power Delivery Network in Next Generation 3D Heterogeneous Integration Architectures

We present a power delivery modeling framework for next generation 3D heterogeneous integration architectures that is based on SiO
2
reconstituted chiplets. We investigate the design trade-offs for steady-state IR-drop to identify the pros and cons of this emerging architecture and explore methods that can help reduce the maximum IR-drop. Compared to conventional 3D TSV-based architectures, this emerging 3D heterogeneous integration architecture can utilize through-oxide-vias, which can directly connect the top die directly to the package. We analyze the benefits of breaking up the embedded-tier into multiple chiplets and observe a decrease in DC-IR drop up to 10%. We identify the limitations of this advanced technology architecture as a function of power dissipation, number of chiplets embedded in bottom-tier, TOV parameters, and hotspot location.