Limits for Dicing Speed Based on Crack Stop Constructions with Different Levels of Robustness

The paper describes how far the optimization of a crack stop design allows the increase of the dicing speed for mechanical dicing. It shows an assessment of yield loss of various crack stop constructions regarding higher dicing speed by using a new test structure approach. The construction of a crack stop determines its robustness. The knowledge of the robustness is important for the definition of the process parameters for chip separation, and is essential e.g. for adjusting the feed speed of the mechanical dicing process. Based on this, the potential for dicing speed increase for the separation concept can be assessed. Basis for this assessment is a new concept of a test vehicle, which is characterized by a defined arrangement of different crack stop designs in one reticle. The reticle was designed in a 130 nm CMOS (complementary metal oxide semiconductor) technology. In the reticle, chips with three different crack stop designs are arranged with an equidistant spacing as a matrix. In all experiments, a standard mechanical dicing process for the selected technology was used, and the yield loss after separation was determined. For these experiments, crack stop constructions were selected, which are described in [1]. The robustness of these crack stop versions was specified by using the AOI-DBA method (automated optical inspection with dedicated binning approach), as described in [1]. This method rates the crack stop robustness as a function of defect numbers in specified zones of the crack stop area. In the experiments, the dicing speed was varied in a defined range between standard value and maximum value to get the correlation of the yield loss and the dicing speed for the investigated crack stop constructions. In the paper, the results of these experiments are presented. The robustness of the analyzed crack stop versions with respect to different dicing speeds is shown. The potential enabled by optimized crack stop version and dicing speed was evaluated. The improvement of the robustness of a crack stop construction is the key factor for refinement of pre-assembly processes. A higher robustness enables the usage of a dicing process with a higher dicing speed. Due to the higher complexity of future wafer technologies, new strategies for a design optimization of crack stops need to be applied. Among these strategies are optimization algorithms in numerical simulations and new approaches by using machine learning.