A Study of Chip-Package Interaction with All-Copper Interconnections on Advanced Glass Substrates

The semiconductor industry is embracing the "Chiplet Revolution," transitioning from monolithic integration to chiplet-based architectures to overcome Moore’s Law limitations. Chiplets, smaller integrated circuits assembled onto a single package substrate, offer flexibility within System-in-Package (SiP) platforms. While architectures utilizing Si interposers or interconnect bridges have become mainstream for high-performance electronic systems, their reliance on an intermediary organic package for board-level attach has positioned glass-panel substrates as a promising alternative to further extend package sizes owing to its superior dimensional stability, high modulus and tailorable coefficient of thermal expansion (CTE). The latter is particularly desirable to balance chip- and board-level reliability while enabling direct surface mount assembly of the advanced glass packages to the printed circuit board. While this CTE mismatch is manageable with compliant solder-based interconnections, the system-level reliability challenge becomes more complex with emerging all-Cu interconnections. With improved pitch scalability, power handling capability and thermal stability, all-Cu interconnections are expected to replace traditional Cu micro-bump interconnections but introduce unprecedented reliability challenges when applied to non-CTE-matched chip-to-package architectures, requiring exploration of novel strategies to improve the reliability of the fragile on-chip back-end-of-line (BEOL) layers. In this study, finite-element modeling was used to assess the risk of crack propagation in these BEOL layers for a chip-on glass-on board architecture employing 10 μm pitch all-Cu chip-to-glass-substrate interconnections. A global-local model approach offers insights into the impact of glass core CTE and gap fill material selection on system-level reliability based on simulated values for strain energy release rate for an interfacial crack in the BEOL and plastic strain in the package-to-board BGA. This highly flexible model can be used to select combinations of geometric and material parameters that allow for simultaneous chip-level and board-level reliability based on pre-established screening criteria such as maximum allowable crack energy release rate, package warpage, and accumulated plastic strain in the BGAs.