Optimization of Core Material Properties for Large Flip-chip Ball Grid Array Substrate to Manage Both Warpage and Board Level Reliability

A large silicon chip or interposer is mounted onto a large package substrate using flip-chip for high performance computing (HPC) such as artificial intelligence (AI) and fifth generation mobile communication systems (5G). Not only the flip-chip joint of the large silicon onto the large substrate but also the ball grid array (BGA) joint of the large package onto the motherboard is important to design board level systems. In fabricating BGA joints, a solder bridge or a non-wet may occur when the warpage of the package is too large. To keep excellent board level reliability (BLR) in temperature cycling (TC) test, reducing stress in BGA joint is important. Therefore, it is a crucial problem to optimize the coefficient of thermal expansion (CTE) of the package substrate between the CTE of silicon and the motherboard. An alternative option would be reducing the stress in BGA by decreasing Young’s modulus of the package substrate. Based on the idea, four core materials made of glass fiber reinforced plastic (GFRP) with different CTE and Young’s modulus, which are (A) conventional resin with E-glass cloth, (B) conventional resin with S-glass cloth, (C) low CTE and high modulus resin with S-glass cloth, and (D) low CTE and low modulus resin with S-glass cloth, were evaluated. A test vehicle with 50-mm-square silicon chip, 100-mm-square package substrate, and 160-mm-square motherboard was designed. The pitch of the flip-chip joint is 0.2 mm and that of the BGA is 1.0 mm. The dimension for the copper stiffener was set at 2.5-mm-thick and 16-mm-width and for the adhesive was set at 0.15-mm-thick to minimize the package warpage. As the result, for the package using the core material (D), the 0.43-mm-warpage at room temperature after flip-chip joint was about two third of the core material (B) and it was reduced to 0.25-mm-warpage by attaching the stiffener. Then, the package was assembled onto the motherboard using a 0.6-mm-diameter solder ball and surface mount technology (SMT) process. Finally, TC test was performed to demonstrate the design concept of the core material (D), which are low CTE and low Young’s modulus. The lifetime of the BLR for the package made of core material (D) is almost the same as that of core material (B).