Ultra Thin Fan-Out 3D WLCSP Heterogeneous Integration Packaging

Heterogeneous integration is the key technology which is applied in HPC, AI and Could computing applications. Through the die to die interconnection, such as ASIC to HBM and ASIC to ASIC. The higher I/O density, wider data transimission bandwidth between memory to active die and lower RC delay are reuqired in chiplet integration. However, the heterogeneous integration between different funtional dies which lead varius process challenges, such as wafer form warpage control, surface coplanarization treatment, and solder joint capability during the die bond (DB) process. Hence, in this paper, we demonstrate the ultra thin Fan-Out RDL heterogeneous integration solution by 3D stacking technologyIn this study, we demonstrate Ultra Thin Fan-out 3D WLCSP packaging with 2 layers RDL by 15/15 um line/space design which pkg thickness can be reduced to smaller than 600um. However, compare to the conventional Fan-out process flow, the glass carrier isn’t required in this FO-3D WLCSP process, it means the process cycle time and cost can be improved significantly in this innovative design. Therefore, the wafer form warpage control and probing methodology are the most challenge process in this structure, we utilized the compatible molding compound and frame form CP testing technology to overcome this challenge sucessfully.This multilayered RDL FO-3D WLCSP packaging without glass carrier technology bring a potential benefit to reduce the packaging form factor and enhance the electrical performance by direct 3D stacking technology, The results of the reliability test including MSL3, TCT 500 cycle and u-HAST 192 hours are qualified in this experiment. Undoubtedly, heterogeneous integration by Fan-Out 3D packaging is the mainstream for the AI and client computing in the IC package industry by utilizing this innovative Multi-layer RDL with the compatible molding compound technology.