Fatigue-Fracture Propensity Measurement and Competing Risk Model for FCBGA Interfaces under Sustained Humidity and Temperature Exposure

The increased electrification of the automotive platform has seen the integration of advanced electronics in various locations for advanced driver assistance systems, including lane departure warning, collision avoidance, cross-traffic alert, obstruction recognition, power management, guidance, navigation, and control. Advanced packaging architectures such as the flip-chip ball grid array have been used to enable much of the advanced processing and memory functions. Under exposure to thermal excursions and humidity in operation, the failures may initiate and propagate, compromising the interfacial integrity and resulting in premature thermal resistance degradation or solder interconnect failure at the chip connections or the package connections. In this paper, the interfacial stress intensity factor has been measured under sustained temperature and sustained humidity exposure for a period of up to 1 year. The measurements have been conducted at various mode mixity using both CNF and ENF specimens. Mode-1 and Mode-2 fracture toughness has been measured. The measurements have been used to fit the Paris Power Law to measure the steady-state crack growth rate and the fatigue exponent. Fracture mechanics have been used to fit the Needleman Damage Law for the computation of the Cohesive Zone damage parameters. A competing risk model has been created for the assessment of the competing risk for failure of multiple interfaces, including the chip-underfill, substrate solder-mask-to-underfill, and thermal interface material-to-copper heat sink interfaces. The results have been validated with experimental data to assess accuracy.